1. Field of the Invention
The present invention relates to a capacitor embedded in a substrate, a method for producing the same, and a circuit board including the capacitor.
2. Description of the Related Art
Along with the rising density of semiconductor devices, a circuit substrate with capacitors embedded has been proposed to meet the needs of reducing the size and thickness of semiconductor devices.
FIG. 1 is a cross-sectional view of a substrate-embedded capacitor of the related art.
The capacitor shown in FIG. 1 is comprised of a substrate 1, a lower electrode 2, a dielectric layer 3, an upper electrode 4, an insulating layer 6, and leader lines 7a and 7b. 
The lower electrode 2, the upper electrode 4, and the dielectric layer 3 sandwiched by the lower electrode 2 and the upper electrode 4 form a capacitor, which possesses an electrical capacitance between the leader lines 7a and 7b. 
FIGS. 2A through 2G are cross-sectional views showing a method for fabricating the substrate-embedded capacitor of the related art.
Next, the method for fabricating the substrate-embedded capacitor is explained with reference to FIGS. 2A through 2G.
First, as shown in FIG. 2A, a silicon wafer is prepared to be used as the substrate 1, on which a number of capacitors are to be fabricated.
Next, as shown in FIG. 2B, the lower electrode 2 is formed for each capacitor to be fabricated on the upper surface of the silicon wafer 1. The lower electrode 2 can be formed, for example, by sputtering platinum (Pt).
Next, as shown in FIG. 2C, the dielectric layer .3 (from a ferroelectric material) is formed on the lower electrode 2. The dielectric layer 3 can be formed, for example, by sputtering BST (Barium Strontium Titanate).
Next, as shown in FIG. 2D, the upper electrode 4 is formed on the dielectric layer 3. The upper electrode 4 can be formed, for example, by sputtering platinum. The lower electrode 2, the upper electrode 4, and the dielectric layer 3 sandwiched by the lower electrode 2 and the upper electrode 4 form a capacitor.
Next, as shown in FIG. 2E, openings 5 are formed in the upper electrode 4 and the dielectric layer 3 to expose the lower electrode 2. The openings 5 can be formed, for example, by dry etching or by laser irradiation.
Next, as shown in FIG. 2F, the insulating layer 6 is formed to cover the upper surface of the upper electrode 4 and the side surfaces and bottoms of the openings 5. The insulating layer 6 can be formed, for example, by sputtering silicon nitride (SiN).
Next, as shown in FIG. 2G, openings 8a are formed in the insulating layer 6 to expose the lower electrode 2, and openings 8b are formed in the insulating layer 6 to expose the upper electrode 4. The openings 8a and 8b can be formed, for example, by dry etching or by laser irradiation. Through the openings 8a and 8b, the leader lines 7a and 7b are connected with the lower electrode 2 and the upper electrode 4, respectively.
Turning to the problem to be solved by the present invention, in the above substrate-embedded capacitor of the related art, the leader lines 7a and 7b of the lower electrode 2 and the upper electrode 4 are connected to the upper side of the substrate 1. This connection requires more space; in addition, there is no other choice for signal line connection; furthermore, the leader lines 7a and 7b themselves become long.
Further, in the above substrate-embedded capacitor of the related art, the semiconductor substrate 1 is thick, so the substrate-embedded capacitor as a whole becomes thick, and consequently, it is difficult to embed the capacitor in a circuit formed in the substrate.